CS Colloquium - Sandhya Dwarkadas, University of Rochester

Event time: 
Thursday, October 10, 2019 - 4:00pm
AKW 200 See map
51 Prospect Street
New Haven, CT 06511
Event description: 

CS Colloquium
Sandhya Dwarkadas, University of Rochester

Host: Abhishek Bhattacharjee

Title: Toward Efficient and Protected Address Translation in Memory Management

Memory management support on state-of-the-art architectures and operating systems encounters performance and protection challenges for today’s applications and execution environments.

In particular, a variety of services, ranging from compilers to web user-interface frameworks (whether on mobile or server platforms), which provide the infrastructure for many high-level applications, suffer from performance degradation due to instruction address translation overheads.

In this talk, I will focus largely on the instruction path to highlight

(1) the impact of instruction address translation on performance (including the importance of using superpages);

(2) the need to rethink protection architectures for performance; and

(3) techniques that enable page table and translation lookaside buffer sharing across applications.

Memory management can also be a source for side channel attacks in compromised operating systems.

I will describe techniques that harden compiler-based approaches to protecting application data from compromised operating systems against page table, last-level cache (LLC), and speculation side-channel attacks.

As time permits, I will also provide a glimpse of ongoing work on sharing-aware resource management for multicore systems with a goal of simultaneously achieving high overall system efficiency and individual application progress guarantees.


Sandhya Dwarkadas is the Albert Arendt Hopeman Professor of Engineering, and Professor and Chair of Computer Science with a secondary appointment in Electrical and Computer Engineering, at University of Rochester, where she has been on the faculty since 1996.

She received her Bachelor’s degree from the Indian Institute of Technology, Madras, India, and her M.S. and Ph.D. from Rice University.

She is a fellow of the ACM and IEEE.

She is also a member of the board and steering committee for the Computing Research Association’s Committee on Widening Participation (CRA-WP).

Her areas of research interest include computer architecture, parallel and distributed systems, and the interaction and interface between the compiler, runtime/operating system, and underlying architecture.

She has made fundamental contributions to the design and implementation of shared memory both in hardware and in software, and to hardware and software energy- and resource-aware configurability.